A well known and prevalently used power semiconductor device is a power MOSFET. FIG. 1 shows a cross-sectional view of a portion of the active region of a power MOSFET according to prior art. The device illustrated by FIG. 1 is of the trench variety. A trench type power MOSFET includes vertical gate structures.
FIG. 2 shows the cross-sectional view of a portion of the active region of a prior art power MOSFET. The device illustrated by FIG. 2 is a planar type device. Such devices include horizontally oriented gate structures.
Referring now to both FIGS. 1 and 2, each device includes source regions 10 each formed in a channel region 12. Gate structures are formed adjacent source regions 10 and the channel region 12 in which the source regions 10 are formed. Each gate structure includes a gate electrode 14, which is typically formed from a conductive polysilicon, and a gate insulation layer 16 which is typically comprised of silicon dioxide. Each gate insulation layer 16 insulates its associated gate electrode 14 from an adjacent channel region 12.
As is well known in the art, in a vertical conduction type MOSFET, channel region 12 is disposed adjacent to drift region 18. Drift region 18 and source regions 10 are of one conductivity while channel region 12 is of the opposite conductivity. Thus, under a range of applied voltages, source regions 10 and drift region 18 are insulated from one another by channel region 12. When an appropriate voltage is applied to a gate electrode 14 a region (invertible channel region or channel) in channel region 12 adjacent its associated gate insulation layer 16 changes conductivity through what is referred to as inversion. As a result, source regions 10 and drift region 18 become electrically connected. Thus, current can be conducted when a voltage is applied between source regions 10 and drift region 18.
In a typical power MOSFET, drain region 18 is epitaxially formed over a semiconductor substrate 20 of the same conductivity, but of a higher concentration of dopants. To allow for external electrical connection drain contact 22 may be electrically connected to substrate 20, and source contact 24 may be electrically connected to source regions 10. It is also well known to connect source contact 24 to a high conductivity contact region 26 of the same conductivity as channel region 12 in order to suppress the possibility of formation of parasitic devices.
FIGS. 1 and 2 show an N channel device in which source regions 10 and drift region 18 have N type conductivity, while channel region 12 has P type conductivity. These conductivity types may be reversed in order to obtain a P channel device.
In a power MOSFET, it is desirable to reduce the resistance of the device during conduction (Rdson). Rdson is primarily determined by the resistance of the channel and the resistance of drift region 18. The resistivity of the drift region is determined by the resistivity and thickness of the epitaxial layer, and is proportional to the breakdown voltage rating of the device. The breakdown voltage rating of the device indicates the ability of the device to withstand breakdown under reverse voltage conditions. Thus, to reduce Rdson the conductivity of the epitaxial layer can be increased, which adversely affects the breakdown voltage rating of the device. Conversely, to improve the breakdown voltage rating the conductivity of the epitaxial layer can be reduced, which increases Rdson. The inverse relationship between Rdson and breakdown voltage rating often forces designers to settle for less than ideal values for the Rdson and the breakdown voltage rating of a device.
A superjunction structure allows the designers to decrease the Rdson of a device without adversely affecting its breakdown voltage. A conventional superjunction device includes alternating P and N type regions below the active cells of the device. The alternating P and N type regions are in substantial charge balance so that under a reverse voltage condition these regions deplete one another thereby allowing the device to withstand breakdown. Thus, a superjunction arrangement allows for an increase in the conductivity of the drain region to improve the Rdson without an affect on the breakdown voltage rating of the device.
FIG. 2 shows a device that includes a superjunction type arrangement. Specifically, FIG. 2 shows a planar type power MOSFET which includes regions 28 of conductivity opposite to that of drift region 18. Regions 28 are in substantial charge balance with drift region 18 in order to form a superjunction.
In a superjunction device of a given breakdown voltage, it is known that Rdson per unit area is reduced as the width (Wp) of regions 28 is reduced. Table 1 is an example of the relationship between Rdson and the width of regions 28. The data show, for example, that at 200 V a device with W(p)=1.5 um has 71% lower Rdson than a device with W(p)=6 um.
TABLE 1WidthEpiEpiDrift R*A% lowerW(p)PitchThicknessResistivitymohm-R*A thanV(um)(um)(um)ohm-cmmm{circumflex over ( )}212 um pitch20061213.81.153192004813.80.7921931%2003613.80.6116947%2002413.80.4211763%2001.5313.80.339271%Thus, for a device such as the one shown in FIG. 2, it is desirable to reduce the pitch (the cell to cell spacing defined by the distance between the center of adjacent trenches).
In a device shown in FIG. 2, a first epitaxial silicon layer 18′ of about 5-10 um and a first conductivity (e.g. N-type) is grown on a silicon substrate 20 of the same conductivity but higher concentration. First epitaxial silicon 18′ is then masked. The mask includes windows that expose portions of first epitaxial silicon 18′ to receive an implant of a second conductivity (e.g. P type) at an energy of about 120 keV. Optionally, the implant is then thermally activated after the masking material is removed.
Next, a second epitaxial silicon 18″ layer is grown on top of first epitaxial silicon 18′ layer. Second epitaxial silicon 18″ is also masked and implanted similar to first epitaxial silicon 18″. If desired third epitaxial silicon 18′″ may be formed, masked and implanted similar to first epitaxial silicon 18′ and second epitaxial silicon 18″. The process may be repeated until a drift region 18 of desired thickness is obtained. Thereafter, a diffusion drive is applied to merge the implants in the vertical direction so that region 28 is formed.
A process for forming a device as shown in FIG. 2 results not only in driving the implants in the vertical direction, but also driving the implants in the horizontal direction. As a result of the process described above, the width of regions 28 is typically greater than 5 um. Consequently, the pitch of a device produced using the above-described process is high. Wide regions 28 are suitable for high voltage devices, but not suitable for low voltage devices due to unacceptably high Rdson.
Other methods have also been suggested for forming superjunction devices. For example, it has been suggested that regions 28 in the device of FIG. 2 can be formed by etching a groove and filling the same with p-type material through, for example, epitaxial deposition. Such a process, however, involves a complicated deep trench etch process, which cannot create the narrow pitch device that is desired. The epitaxial growth process in the trench also introduces defects and can possibly compromise the reliability of the device.
Another suggested method is forming regions 28 through selective neutron transmutation doping. This process, however, is not commonly used or available for power MOSFET fabrication.
Yet another suggested method involves forming a deep trench, doping the sidewalls of the trench to form regions 28, and then filling the trench with a dielectric material. This process can possibly provide narrow pitch devices, but still requires deep trenches to be etched in the silicon, and the sidewalls to be doped in a defined manner. It is doubtful that this doping can be controlled well.